DiComLab
  Digital Communications Laboratory
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Working areas | Public Funding | Private contracts | Journal papers | Conference papers


Research 

The main research line is the development of algorithms and architectures for implementing digital signal processing and communication systems on FPGA.

Working areas


ADVANCED FORWARD ERROR CORRECTION

The objective of this research is the development of algorithms and architectures for hardware implementation of FEC blocks that will be required in future communications systems.

We have focused in:

  • Binary Low-Density Parity-Check codes decoders
  • Non-binary Low-Density Parity-Check codes decoders
  • Soft decoding of Reed-Solomon codes.

We want to improve the operation of the LDPC decoders for high SNRs where the error-floor can appears. We have developed an FPGA-based hardware LDPC emulator to accelerate simulations for very low bit rates.


OFDM-BASED OPTICAL COMMUNICATIONS SYSTEMS

The use of the OFDM modulation in optical communication has attracted a high interest in recent years thanks to the possibility of simple equalization with moderate implementation complexity using digital signal processing techniques. The objectives of this research line are:

  • Development of algorithms for direct detection optical OFDM
  • Analysis and evaluation of nonlinear optical effects in optical OFDM
  • Implementation of a real-time demonstrator using high speed data converters (Gsps)


FPGA-BASED SOFTWARE RADIOS

Algorithms and architectures for FPGA-based software radios Algorithms and architectures to implement digital communication systems in FPGA devices:

  • Re-sampling for transmission
  • Digital up & down conversion
  • Synchronization for QAM systems
  • Synchronization for OFDM systems
  • Digitally implemented analog modulations

Three FPGA-based demonstrators have been developed:


FPGA-BASED DSP FOR ULTRASOUND WAVES

Ultrasounds are used in non-destructive measurements in nuclear and aeronautic sectors. This line is focused in the design of digital signal processing algorithms for ultrasound waves and their hardware architectures for FPGA devices:

  • FIR and IIR Filters
  • Multirate filters
  • Pipeline-interleaved filters
  • Envelope detectors
  • Logarithmic converters
  • Interpolators for Giga-sample operation
  • Beanforming for array sensors

This R&D line is developed for the company TECNATOM under the contract “Desarrolllos de tecnologías electrónicas”.


ARITHMETIC AND DSP FOR FPGA

Design of arithmetic operators and digital signal processing kernels optimized for their implementation in Altera and Xilinx FPGA devices.


Projects (public funding)

  • Title: Digital processing of optical signals in waveguides (OPTOPRO)
    Support: Spanish Ministry of Science and Innovation. Grant: TEC2012-38558-C02-02
    Period: 2013-2015

  • Title: FEC algorithms and architectures for future communication systems
    Support: Spanish Ministry of Science and Innovation. Grant: TEC2011-27916
    Period: 2012-2014

  • Title: Optic OFDM
    Support: Politechnic University of Valencia
    Period: 2010-2011

  • Title: FEC architectures for very high throughput communication systems
    Support: Spanish Ministry of Science and Innovation. Grant: TEC2008-06787
    Period: 2009-2011

  • Title: Advanced algorithms for error correction
    Support: Spanish Ministry of Industry. Grant: TSI-020100-2008-141
    Period: 2008-2009

  • Title: FPGA implementation of algorithms for broadband wireless communication systems
    Support: Spanish Ministry of Education and Science. Grant: TEC2005-08406-C03-01
    Period: 2006-2008

  • Title: Reconfigurable Hardware in broadband communication systems
    Support: Generalitat Valenciana. Grant: GV06/114
    Period: 2006-2007

  • Title: Design of optimized IP cores for OFDM-based wireless LAN
    Support: Spanish Ministry of Science and Tecnology. Grant: TIC2001-2688-C03
    Period: 2002-2004

  • Title: Design on FPGA of communication circuits
    Support: Generalitat Valenciana. Grant: GV00-093-14
    Period: 2001-2002

  • Title: Design of custom digital signal processors
    Support: Politechnic University of Valencia
    Period: 2000-2001


Projects (private contracts)

  • Title: Design and FPGA implementation of functions for an interference-canceler receiver
    Payer: INDRA SISTEMAS
    Period: 2013-2014

  • Title: Development of electronic technologies
    Payer: TECNATOM
    Period: 2010-2014

  • Title: Development of a CMA Equalizer core
    Payer: ERZIA TECHNOLOGIES, S.L.
    Period: 2012

  • Title: Synchronization algorithms for a DS-SS MODEM
    Payer: INDRA ESPACIO
    Period: 2010-2011

  • Title: Detailed design and FPGA implementation of a high speed MODEM
    Payer: INDRA ESPACIO
    Period: 2007-2008

  • Title: Detailed design and FPGA implementation of functions for a Spread Spectrum In Orbit Test MODEM
    Payer: INDRA ESPACIO
    Period: 2006-2007

  • Title: Design and FPGA implementation of a receiver for DSRC (Dedicated Short-Range Communications)
    Payer: INDRA ESPACIO
    Period: 2006

Journal papers

  • J.O. Lacruz, F. Garcia-Herrero, M.J. Canet, J. Valls,“Reduced-complexity Non-Binary LDPC decoder for high-order Galois fields based on Trellis Min-Max algorithm, ” IEEE Transactions on Very Large Scale Integration, accepted for publication in 2015
  • J.O. Lacruz, F. Garcia-Herrero, M.J. Canet, J. Valls,“High-performance NB-LDPC decoder with reduction of message exchange, ” IEEE Transactions on Very Large Scale Integration, accepted for publication in 2015
  • J.S. Bruno, V. Almenar, J. Valls, J.L. Corral,“Low-Complexity Time Synchronization Algorithm for Optical OFDM PON System Using a Directly Modulated DFB Laser, ” Journal of Optical Communications and Networking, Vol.7, No. 11, pp.1025-1033, Nov. 2015
  • J.O. Lacruz, F. Garcia-Herrero, J. Valls,“Reduction of complexity for Non-binary LDPC decoders with compressed messages, ” IEEE Transactions on Very Large Scale Integration, Vol.23, No.11, pp.2676-2679, Nov. 2015
  • P. Medina, V. Almenar, J.L. Corral,“Combined Data Detection Scheme for Zero-Padded OFDM Signals in MMF Links , ” IEEE Photonics Technology Letters, Vol. 27, No. 16, pp. 1753-1756, Jul. 2015
  • J.O. Lacruz, F. Garcia-Herrero, D. Declercq, J. Valls, "One Minimum Only Trellis Decoder for Non-Binary Low-Density Parity-Check Codes, " IEEE Transactions on Circuits and Systems I, Vol.62, No.1, pp.177-184, Jan. 2015
  • J.O. Lacruz, F. Garcia-Herrero, D. Declercq, J. Valls, "Simplified Trellis Min-Max Decoder Architecture for Nonbinary Low-Density Parity-Check Codes, " IEEE Transactions on Very Large Scale Integration, Vol.23, No.9, pp.1783-1792, Sep. 2015
  • J.M. Catala, F. Garcia-Herrero, J. Valls, K. Liu, S. Lin, “Reliability-based iterative decoding algorithm for LDPC codes with low variable-node degree, ” IEEE Communications Letters, Vol.18, No.12, pp.2065-2268, Dic. 2014
  • F. Garcia-Herrero, E. Li, D. Declercq, J. Valls, "Multiple-Vote Symbol-Flipping Decoder for Non-Binary LDPC Codes, " IEEE Transactions on Very Large Scale Integration, Vol.22, No.11, pp.2256-2267, Nov. 2014
  • P. Medina, V. Almenar, J.L. Corral,“Evaluation of optical ZP-OFDM transmission performance in multimode fiber links, ” Optics Express, Vol. 22, No. 1, pp. 1008-1017, Ene. 2014
  • F. Garcia-Herrero, D. Declercq, J.Valls, “Non-Binary LDPC Decoder based on Symbol Flipping with Multiple Votes, ” IEEE Communications Letters, Vol.18 No.5, pp.749-752, Jun.2014
  • F. Angarita, J. Valls, V. Almenar, V. Torres, "Reduced-Complexity Min-Sum Algorithm for Decoding LDPC Codes with Low Error-Floor, ", IEEE Transactions on Circuits and Systems I, Vol.61, No.7, pp.2150-2158, Jul. 2014
  • F. Garcia-Herrero, M.J. Canet, J. Valls, "Non-Binary LDPC Decoder Based on Simplified Enhanced Generalized Bit Flipping Algorithm, " IEEE Transactions on Very Large Scale Integration, Vol.22, No.6, pp.1455-1459, Jun. 2014
  • F. Garcia-Herrero, M.J. Canet, J. Valls, “Architecture of Generalized Bit-Flipping Decoding for High-Rate Non-binary LDPC Codes, ” Circuits, Systems, and Signal Processing, Vol. 32, pp: 727-741, 2013
  • G.A. Jaquenod, J. Valls, J. Siman, “Efficient FPGA Hardware Reuse in a Multiplierless Decimation Chain, ” International Journal of Reconfigurable Computing, accepted for publication in 2013
  • Sandra Roger, Alberto Gonzalez, Vicenç Almenar, Gerald Matz, “An Efficient Fixed-Complexity Sphere Decoder with Quantized Soft Outputs, ” IEEE Communication Letters, to be published, 2012
  • Sandra Roger, Carla Ramiro, Alberto Gonzalez, Vicenç Almenar, Antonio M. Vidal, “An Efficient GPU Implementation of Fixed-Complexity Sphere Decoders for MIMO Wireless Systems, ” Integrated Computer-Aided Engineering, Vol.19, No.4, pp.341-350, 2012
  • Sandra Roger, Carla Ramiro, Alberto Gonzalez, Vicenç Almenar, Antonio M. Vidal, “Fully parallel GPU implementation of a fixed-complexity soft-output MIMO detector, ” IEEE Trans. on Vehicular Technology, Vol.61, No.6, pp.3796-3800, Oct.2012
  • F. Angarita, J. Marin-Roig, V. Almenar, J. Valls, “Low-complexity LDPC decoding algorithm for high-speed VLSI implementation, ” IET Communications, Vol.6, No.16, pp.2575-2581, Nov.2012
  • R. Gutierrez, V. Torres, J.Valls, “Hardware Architecture of a Gaussian Noise Generator Based on Inversion Method, ” IEEE Transactions on Circuits & Systems II, Vol.59, No.8, pp.501-505, 2012
  • F. Garcia-Herrero, M.J. Canet, J.Valls, M.Flanagan, “Serial Symbol-Reliability Based Algorithm For Decoding Non-Binary LDPC Codes, ” IEEE Communications Letters, Vol.16 No.6, pp.909-912, Jun.2012
  • M.J. Canet, J.Valls, V.Almenar, J. Marin-Roig, “FPGA implementation of an OFDM-based WLAN receiver, ” Microprocessors and Microsystems, Vol.36, No.3, pp.232-244, 2012
  • M.J. Canet, V.Almenar, S. Flores, J.Valls, “Low complexity time synchronization algorithm for OFDM systems with repetitive preambles, ” Journal of Signal Processing Systems, Vol.68, No.3, pp.287-301, Sep.2012
  • F. Angarita, T.Sansaloni, A. Perez-Pascual, J. Valls, “Modifed Shuffled Based Architecture for High Throughput Decoding of LDPC Codes, ” Journal of Signal Processing Systems, Vol.68, No.2, pp.139-149, Aug.2012
  • Sandra Roger, Alberto Gonzalez, Vicenç Almenar, Antonio M. Vidal, “Practical aspects of preprocessing techniques for K-best tree search MIMO detectors, ” Computers & Electrical Engineering, Vol.37, No.4, pp.451-460, Jul.2011
  • V. Almenar, A. Girona, S. Flores, J. Marin-Roig, “Transmit diversity scheme for OFDM systems using the odd DFT, ” IEICE Transactions on Communications, Vol.E94-B, No.8, pp.2411-2413, Aug.2011
  • F. Garcia-Herrero, M.J. Canet, J. Valls, P.K. Meher, “High-Throughput Interpolator Architecture for Low-Complexity Chase Decoding of RS Codes, ” IEEE Transactions on Very Large Scale Integration, Vol.20, No.3, pp.568-573, Mar.2012
  • F. Angarita, T.Sansaloni, M.J.Canet, J. Valls, “Improved Sliced Message Passing Architecture for High Throughput Decoding of LDPC Codes, ” Journal of Signal Processing Systems, Vol.66, No.2, pp.99-104, Feb.2012
  • F. Garcia-Herrero, J. Valls, P.K. Meher, “High speed RS(255,239) decoder based on LCC decoding, ” Circuits, Systems, and Signal Processing, Vol.30, No.6, pp.1643-1669, May.2011
  • R. Gutierrez, J. Valls, “Low cost Hardware Implementation of logarithm approximation, ” IEEE Transactions on Very Large Scale Integration, Vol.19, No.12, pp.2326-2330, Dic.2011
  • F. J. Martínez-Zaldívar, A. M. Vidal-Maciá, A. Gonzalez and V. Almenar, “Tridimensional block multiword LDPC decoding on GPUs, ” The Journal of Supercomputing, Vol.58, pp.514-322, 2011
  • Sandra Roger, Alberto Gonzalez, Vicenç Almenar, Antonio M. Vidal, “Extended LLL algorithm for efficient signal precoding in multiuser nication systems, ” IEEE Communications Letters, Vol.14, No.3, Mar.2010
  • R. Gutierrez, V. Torres, J. Valls, “FPGA implementation of atan(Y/X) based on Logarithmic transformation and LUT-based techniques, ” Journal of Systems Architecture, Vol.56, pp.588-596, Nov.2010
  • Pramod K. Meher, Javier Valls, Tso-Bing Juang, K. Sridharan, and Koushik Maharatna, “50 Years of CORDIC: Algorithms, Architectures and Applications, ” IEEE Transactions on Circuits and Systems I, Vol.56, No.9, Sep.2009
  • Sandra Roger, Alberto Gonzalez, Vicenç Almenar, Antonio M. Vidal, “MIMO Channel Matrix Condition Number Estimation and Threshold Selection for Combined K-Best Sphere Decoders, ” IEICE Transactions on Communications Vol.E92-B (4), pp.1380-1383, Apr.2009
  • F. Angarita, A. Almenar, M.J. Canet, T. Sansaloni, J.Valls, “Power consumption reduction in a Viterbi Decoder for OFDM-WLAN, ” Journal of Circuits, Systems and Computers Vol.18, No.7, pp.1333-1337, Nov. 2009
  • A. Perez-Pascual, V. Torres, T. Sansaloni, V. Almenar, J.Valls, “Design of Power and Area Efficient Digital Down-converters for Broadband Communications Systems, ” Journal of Signal Processing Systems Vol.56, No.1, pp.35-40, Jul.2009
  • R. Gutierrez, J.Valls, “Low-power FPGA-implementation of atan(Y/X) using Look-Up Table methods for communication applications, ” Journal of Signal Processing Systems Vol.56, No.1, pp.26-33, Jul.2009
  • V. Torres, A. Perez-Pascual, T. Sansaloni, J.Valls, “Design and FPGA-implementation of a high performance timing recovery loop for broadband communications, ” Journal of Signal Processing Systems Vol.56, No.1, pp.17-23, Jul.2009
  • F. Angarita, M.J. Canet, T. Sansaloni, A. Perez-Pascual, J.Valls, “Efficient mapping of CORDIC Algorithm for OFDM-based WLAN, ” Journal of Signal Processing Systems,Vol.52, No.2, pp.181-191, Aug.2008
  • F. Angarita, M.J. Canet, T. Sansaloni, V. Almenar, J.Valls, “Architectures for the implementation of a OFDM-WLAN Viterbi Decoder, ” Journal of Signal Processing Systems, Vol.52, No.1, pp.35-44, Jul.2008
  • T. Sansaloni, A. Perez-Pascual, V. Torres, J.Valls, “Scheme for reducing the storage requirements of FFT twiddle factors on FPGAs, ” Journal of VLSI Signal Processing, Vol.47, pp.105-115, May.2007
  • T. Sansaloni, A. Perez-Pascual, V. Torres, V. Almenar, J. Toledo, J.Valls, “FFT Spectrum Analyzer Project for Teaching Digital Signal Processing with FPGA devices, ” IEEE Trans. on Education, Nov.2007
  • F. Castells, V. Almenar, “Closed-form expression for the BER of m-QAM-OFDM systems over time and frequency-selective wireless channels, ” International Journal of Communication Systems, Vol.19(8), pp.861-876, Oct.2006
  • J.Valls, T. Sansaloni, A. Perez-Pascual, V. Torres, V. Almenar, “The use of CORDIC in Software Defined Radios: A tutorial, ” IEEE Communications Magazine, Vol.44, No.9, Sep.2006
  • T. Sansaloni, A. Perez-Pascual, V. Torres, J. Valls, “Efficient pipeline FFT processor form MIMO-OFDM systems, ” Electronic Letters, Vol.41, No.19, Sep.2005
  • T. Sansaloni, A. Perez-Pascual, J. Valls, “Area-efficient FPGA-based FFT processor, ” Electronic Letters, Vol.39, No.19, Sep.2003
  • J. Valls and E. Boemo, “Efficient FPGA-Implementation of two's complement digit-serial/parallel multipliers, ” IEEE Transactions on Circuits and Systems II, Vol.50, No.6, Jun.2003
  • F. Cardells, J. Valls, “Area-Optimized Implementation of Quadrature Direct Digital Frequency Synthesizers on LUT-based FPGAs, ” IEEE Transactions on Circuits and Systems II, Vol.50, No.3, Mar.2003
  • T. Sansaloni, J. Valls, K.K. Parhi, “Digit-serial Complex-Number Multipliers on FPGAs, ” Journal of VLSI Signal Processing, special issue on Computer Arithmetic and Applications, Vol.33, No.1-2, pp.105-115, Jan.2003
  • J. Valls, M. Kuhlmann, K.K. Parhi, “Evaluation of CORDIC Algorithms for FPGA design, ” Journal of VLSI Signal Processing, Vol.32, No.3, pp.207-222, Nov.2002
  • F. Cardells, J. Valls, “Optimization of direct digital frequency synthesizers based on CORDIC, ” Electronic Letters, Vol.37, No.21, pp.1278-1280, Oct.2001

Conference papers

  • F. Garcia-Herrero, D. Declercq, J. Valls, “ A symbol flipping decoder for NB-LDPC relying on multiple votes, ” 2014 8th International Symposium on Turbo Codes and Iterative Information Processing (ISTC), Bremen, Germany, Aug.2014
  • E. Li, D. Declercq, F. Garcia-Herrero, J. Omar, J. Valls, “ Low latency T-EMS decoder for NB-LDPC codes, ” Asilomar Conference on Signals, Systems and Computers, Pacific Grove, CA, USA, Nov.2013
  • F Garcia-Herrero, MJ. Canet, J. Valls, “ High-speed NB-LDPC decoder for wireless applications, ” Int.Symposium on Intelillent Signal Processing and Communication Systems (ISPACS), Okinawa, Japan, Nov.2013
  • V. Torres, A. Perez-Pascual, T. Sansaloni, J. Valls, “Fully-parallel LUT-based (2048,1723) LDPC Code Decoder for FPGA, ” IEEE International Conference on Electronics, Circuits and Systems (ICECS), Sevilla, Spain, Dec.2012
  • F. Angarita, V. Torres, A. Perez-Pascual, J. Valls, “High-Throughput FPGA-based Emulator for Structured LDPC Codes, ” IEEE International Conference on Electronics, Circuits and Systems (ICECS), Sevilla, Spain, Dec.2012
  • F. Garcia-Herrero, M.J. Canet, J. Valls, “Decoder for an Enhanced Serial Generalized Bit Flipping Algorithm, ” IEEE International Conference on Electronics, Circuits and Systems (ICECS), Sevilla, Spain, Dec.2012
  • R. Gutierrez, J. Valls, A. Perez-Pascual, “FPGA-implementation of time-multiplexed multiple constant multiplication based on carry-save arithmetic, ” International Conference in Field Programmable Logic and Applications (FPL), Prague, Czech Republic, Aug.2009
  • J. Marín-Roig, V. Almenar, M.J. Canet, J. Valls, “64-QAM 4x4 MIMO Decoders Based on Successive Projection Algorithm, ” IEEE International Conference on Electronics, Circuits and Systems (ICECS), Malta, Aug.2008
  • F. Angarita, M.J. Canet, T. Sansaloni, V. Almenar and J. Valls, “Reduction of power consumption in a Viterbi Decoder for OFDM-WLAN, ” IEEE International Conference on Electronics, Circuits and Systems (ICECS), Marrakech, Morocco, Dec.2007
  • M.J. Canet, V. Almenar, J. Marin-Roig, J. Valls, “Time synchronization for the IEEE 802.11a/g WLAN Standard, ” 8th IEEE Annual International Symposium on Personal Indoor and Mobile Radio Communications (PIMRC), Athens, Greece, Sep.2007
  • M.J. Canet, V. Almenar, S. Flores, J. Valls, “Improvement of a Time Synchronization Algorithm for IEEE 802.11a/G WLAN Standard, ” 15th European Signal Processing Conference (EUSIPCO), Poznan, Poland, Sep.2007
  • R. Gutierrez, J. Valls, “Implementation on FPGA of a LUT-based atan(Y/X) operator suitable for Synchronization Algorithms, ” International Conference in Field Programmable Logic and Applications (FPL), Amsterdam, Holland, Aug.2007
  • V. Torres, T. Sansaloni, A. Perez-Pascual, J. Valls, “Design of high performance timing recovery loops for communication applications, ” 2006 IEEE Workshop on Signal Procesing Systems (SiPS), Banff, Canada, Nov.2006
  • M.J.Canet, I. Wassel, V. Almenar, J. Valls, “Performance evaluation of fine time synchronizer for WLANs, ” 13th european Conference on Signal Processing (EUSIPCO), Antalya, Turkey, Sep.2005
  • F. Angarita, T. Sansaloni, A. Pérez-Pascual, J. Valls, “FPGA-based design of a Viterbi decoder for WLAN, ” 2005 IEEE Workshop on Signal Processing Systems (SiPS), Atenas, Greece, Nov.2005
  • F. Angarita, T. Sansaloni, A. Pérez-Pascual, J. Valls, “Efficient FPGA implementation of CORDIC algorithm for circular and linear coordinates, ” International Conference in Field Programmable Logic and Applications (FPL), Tampere, Finland, Ago.2005
  • T. Todorovich, E. Boemo, F. Angarita, J. valls, “Statical power estimation for FPGAs, ” International Conference on Field Programmable Logic and Applications (FPL), Tampere, Finland, Ago.2005
  • MJ.Canet, F. Vicedo, V. Almenar, J. Valls, “FPGA imlementation of an IF transceiver for OFDM-based WLAN, ” 2004 IEEE Workshop on Signal Processing Systems (SiPS 2004), Austin, Texas, Aug.2004
  • M.J.Canet, F. Vicedo, V. Almenar, J. Valls, E.R. De Lima, “Hardware Design of a FPGA-Based Synchronizer for Hiperlan/2, ” International Conference in Field Programmable Logic and Applications (FPL), Antwerp, Belgium, Aug.2004
  • MJ. Canet, F. Vicedo, J. Valls, V. Almenar, “A common FPGA-based synchronizer architecture for hiperlan 2 and IEEE 802.11A WLAN systems, ” 15th International Symposium on Personal, Indoor and Mobile Radio Communications (PIMRC), Barcelona, Spain, Sep.2004
  • M.J.Canet, F. Vicedo, V. Almenar, J. Valls, E.R. De Lima, “Implementation of a Synchronizer for Hiperlan/2 on FPGA, ” International  Workshop on Telecommunications (IWT), Santa Rita do Sapucai, Brazil, Aug.2004
  • MJ. Canet, F. Vicedo, J. Valls, V. Almenar, “Design of a digital front-end transmitterfor OFDM-WLAN systems using FPGA, ” First International Symposium on Control, Communications and Signal Processing (ISCCSP), Hammamet, Tunisia, Mar.2004
  • E.R. de Lima, S.J. Flores, V. ALmenar, M.J. Canet, “Peformance Enhancements in OFDM-WLAN Systems Using MIMO Access Techniques, ” International Workshop on Telecommunications (IWT), Santa Rita do Sapucai, Brazil, Aug.2004
  • E.R. de Lima, S.J. Flores, V. ALmenar, M.J. Canet, “Performance Evaluation of MIMO-OFDM Systems Using Sphere Decoding Algorithm, ” The 60th Vehicular Technology Conference (VTC), Los Angeles, USA, Sep.2004
  • E.R. de Lima, S.J. Flores, V. ALmenar, M.J. Canet, “Analysis and Contrast between STC and Spatial Diversity Techniques for OFDM WLAN with Channel Estimation, ” International Conference on Telecommunications (ICT), Fortaleza, Brasil, Aug.2004
  • F. Cardells, J. Valls, “Quadrature Direct Digital Frequency Synthesizers: Area-optimized Design Map for LUT-based FPGAs, ” IEEE International Symposium on Circuits and Systems (ISCAS), Bangkok, Thailand, May.2003
  • J. Marín-Roig, V.Torres, M.J.Canet, A.Pérez, T. Sansaloni, F. Cardells, F.Angarita, F.Vicedo, V.Almenar, J.Valls, “DIGIMOD: A tool to implement FPGA-based digital IF and baseband modems, ” International Conference on Field Programmable Logic and Applications (FPL), Lisbon, Portugal, Sep.2003
  • F. Cardells, J. Valls, V. Almenar, “Symbol Timing Synchronization in FPGA-based Software Radios: Application to DVB-S, ” 13th International Conference on Field Programmable Logic and Applications (FPL), Lisbon, Portugal, Sep.2003
  • F. Cardells, A. Perez-Pascual, V. Torres, J. Valls, V. Almenar, “Design of a DVB-S receiver in FPGA, ” 2003 IEEE Workshop on Signal Processing Systems (SiPS), Seoul, Korea, Aug.2003
  • J. Marín-Roig, V.Torres, M.J.Canet, A.Pérez, T. Sansaloni, F. Cardells, F.Angarita, F.Vicedo, V.Almenar, J.Valls, “DIGIMOD: A tool to implement FPGA-based digital front-end for software radios, ” Software Defined Radio Technical Conference and Product Exposition (SDR), Orlando, Florida, Nov.2003
  • F. Cardells, J. Valls, V. Almenar, V. Torres, “Efficient FPGA-based QPSK Demodulation Loops: Application to the DVB standard, ” International Conference on Field Programmable Logic and Applications (FPL), Montpellier, France, Sep.2002
  • F. Cardells, J. Valls, “High Performance Quadrature Digital Mixers for FPGAs, ” International Conference on Field Programmable Logic and Applications (FPL), Montpellier, France, Sep.2002
  • José Marin-Roig, Javier Valls, Vicenç Almenar, “LUT-based Up-converters for FPGA, ” IEEE, IET International Symposium on Communication Systems, Networks and Digital Signal Processing Conference, Staffordshire, UK, Jul.2002
  • F. Cardells, J. Valls, “Optimized FPGA-implementation of quadrature DDS, ” IEEE International Symposium on Circuits and Systems (ISCAS), Arizona, USA, May.2002
  • A. Perez-Pascual, T. Sansaloni, J. Valls, “FPGA Based Radix-4 Butterflies for HIPERLAN/2, ” IEEE International Symposium on Circuits and Systems (ISCAS) Arizona, USA, May.2002
  • T. Sansaloni, A. Perez-Pascual, J. Valls, “Distributed Arithmetic Radix-2 Butterflies for FPGA, ” International IEEE Conference on Electronics, Circuits, and Systems (ICECS) (ICECS 2001)
  • A. Perez-Pascual, T. Sansaloni, J. Valls, “FPGA Based On-line Complex-Number Multipliers, ” International IEEE Conference on Electronics, Circuits, and Systems Malta, Sep.2001
  • J. Valls, M. Kuhlmann, K.K. Parhi, “Efficient mapping of CORDIC algorithms on FPGA, ” 2000 IEEE Workshop on Signal Processing Systems (SiPS), Louisiana, USA, Oct.2000
  • T. Sansaloni, J. Valls, K.K. Parhi, “Digit-Serial Fixed Coefficient Complex Number Multiplier-Accumulator on FPGAs, ” Annual IEEE International ASIC/SOC Conference, Washington, USA, Sep.2000
  • T. Sansaloni, and J. Valls, “FPGA-Based Digit-Serial Radix 2 Butterflies, ” IASTED International Conference Signal Processing and Communications (SPC), Marbella, Spain, Sep.2000
  • A. Pérez-Pascual, and J. Valls, “Radix-4 On-Line Complex-Number Multiplier, ” IASTED International Conference Signal Processing and Communications (SPC), Marbella, Spain, Sep.2000
  • T. Sansaloni, J. Valls, K.K. Parhi, “FPGA-based Digit-Serial Complex Number Multiplier-Accumulator, ” IEEE International Symposium on Circuits and Systems (ISCAS) Geneva, Switzerland. May.2000
  • J.Valls, T.Sansaloni, M.M.Peiró, E.Boemo, “Fast FPGA-Based Pipelined Digit-Serial/Parallel Multipliers, ” IEEE International Symposium on Circuits and Systems (ISCAS), Orlando, USA, Jun.1999
  • A.P. Pascual, J.Valls, M. Martínez, “Efficient Complex-Number Multipliers mapped on FPGA, ” IEEE International Conference on Electronics, Circuits and Systems (ICECS), Chipre, Sep.1999.>
  • T. Sansaloni, J.Valls, M.J. Canet, M. Martínez, “FPGA-based notch filter for cancelling 50Hz noise on ECGs, ” Design of Circuits and Integrated Systems Conference (DCIS), Mallorca, Spain, Nov.1999
  • M. M. Peiró, J. Valls, T. Sansaloni , A.P. Pascual, E. Boemo, “A Comparison between Lattice, Cascade and Direc-form FIR Filter Structures by using an FPGA Bit-serial Distributed Arithmetic Implementation, ” IEEE International Conference on Electronics, Circuits and Systems (ICECS), Chipre, Sep.1999
  • J.Valls, M. Martínez, T. Sansaloni, E. Boemo, “Design and FPGA implementation of Digit-Serial FIR filters, ” 5th IEEE International Conference on Electronics, Circuits and Systems (ICECS), Lisbon, Portugal, Sep.1998
  • J.Valls, M. Martínez, T. Sansaloni, E. Boemo, “A Study About FPGA-based Digital Filters, ” IEEE Workshop on Signal Processing Systems: Design and Implementation (SiPS), Boston, USA, Oct.1998
  • J.Valls, M. Martínez, T. Sansaloni, E. Boemo, “Custom Digit-Serial DSPs on Altera FPGAs, ” Design of Circuits and Integrated Systems Conference (DCIS), Madrid, Spain, Nov.1998
  • M. Martínez, J.Valls,  T. Sansaloni, E. Boemo, “High-Level Synthesis of Custom DSP Blocks using Distributed Arithmetic, ” Design of Circuits and Integrated Systems Conference (DCIS), Madrid, Spain, Nov.1998
  • M. Martínez, J.Valls, E. Boemo, “On the design of PFGA-based multioperand pipeline adders, ” Design of Circuits and Integrated Systems Conference (DCIS), Sevilla, Spain, Nov.1997


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