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Investigación | Personal | Proyectos | Convenios | Cursos doctorado | Cursos a empresas | Tesis doctorales | Publicaciones


Grupo de Integración de Sistemas Electrónicos Digitales (GISED)

El Grupo de Integración de Sistemas Digitales está formado por profesores del Departamento de Ingeniería Electrónica de la Universidad Politécnica de Valencia. Sus actividades se desarrollan en el Laboratorio de Comunicaciones Digitales de la Escuela Politécnica superior de Gandia.

Investigación

Nuestra investigación se centra en el diseño e implementación en dispositivos FPGA de arquitecturas para sistemas de procesado digital de la señal. Concretamente estamos trabajando con los algoritmos que se requieren en los sistemas de comunicaciones de banda ancha.

Las áreas actuales de trabajo son:

  • Sistemas basados en OFDM
  • Sincronización en sistemas monoportadora de banda ancha
  • Arquitecturas para sistemas MIMO (Multi-Input Multi-Output)
  • Algoritmos avanzados para la correción de errores
  • Operadores aritméticos de altas prestaciones

Disponemos de una librería de cores-IP para facilitar el prototipado rápido de sistemas de comunicacniones en FPGA. Hemos desarrollado varios demostradores hardware de sistemas de procesado digital de la señal y de comunicaciones basados en FPGAs:

Personal

Proyectos de I+D

  • Título: Algoritmos y arquitecturas de FEC para futuros sistemas de comunicaciones
    Entidad financiadora: Ministerio de Ciencia e Innovación. Ref: TEC2011-27916
    Periodo: 2012-2014

  • Título: Arquitecturas de FEC para sistemas de comunicaciones de muy alta velocidad
    Entidad financiadora: Ministerio de Ciencia e Innovación. Ref: TEC2008-06787
    Periodo: 2009-2011

  • Título: Algoritmos Avanzados de Corrección de Errores: ALCE
    Entidad financiadora: Ministerio de Industria Turismo y Comercio. Ref: TSI-020100-2008-141
    Periodo: 2008-2009

  • Título: Implementación en FPGA de algoritmos para sistemas de comunicaciones inalámbricas de banda ancha.
    Entidad financiadora: Ministerio de Educación y Ciencia. Ref: TEC2005-08406-C03-01
    Periodo: 2006-2008

  • Título: Hardware reconfigurable en sistemas de comunicaciones de banda ancha
    Entidad financiadora: Generalitat Valenciana. Ref: GV06/114
    Periodo: 2006-2007

  • Título: Diseño de cores-IP para redes inalámbricas basadas en OFDM. Optimización en área en la estación base.
    Entidad financiadora: Ministerio de Ciencia y Tecnología. Ref: TIC2001-2688-C03-02
    Periodo: 2002-2004

  • Título: Diseño eficiente de circuitos para telecomunicaciones en FPGA
    Entidad financiadora: Generalitat Valenciana. Ref: GV00-093-14
    Periodo: 2001-2002

  • Título: Diseño de procesadores digitales de señal a medida
    Entidad financiadora: Universidad Politécnica de Valencia
    Periodo: 2000-2001

Proyectos de I+D con empresas

  • Título: Diseño e implementación en FPGAs de funciones para un receptor con cancelación de interferencias
    Entidad: INDRA SISTEMAS S.A.
    Periodo: 2013 - 2014

  • Título: Desarrollo de tecnologías electrónicas
    Entidad: TECNATOM S.A.
    Periodo: 2010-2014

  • Título: Algoritmos de sincronización para MODEM DS-SS
    Entidad: INDRA ESPACIO S.A.
    Periodo: 2010 - 2011

  • Título: Desarrollo de módulos DSP para la electrónica de ultrasonidos F1
    Entidad: TECNATOM S.A.
    Periodo: 2008-2010

  • Título: Diseño detallado e implementación en FPGA de un modem de alta velocidad
    Entidad: INDRA ESPACIO S.A.
    Periodo: Septiembre 2007 - 2008

  • Título: Diseño detallado e implementación en FPGA de funciones del MODEM SS IOT (Spread Spectrum In Orbit Test)
    Entidad: INDRA ESPACIO S.A.
    Periodo: Septiembre 2006 - 2007

  • Título: Diseño e implementación en FPGA de un receptor para DSRC (Dedicated Short-Range Communications)
    Entidad: INDRA ESPACIO S.A.
    Periodo: Agosto-Noviembre de 2006

Cursos de doctorado

El grupo imparte dos asignaturas en el Master de Ingeniería en Sistemas Electrónicos del Departamento de Ingeniería Electrónica:
  • Título: Tratamiento digital de la señal en FPGA
  • Título: Implementación de sistemas de comunicaciones digitales
También imparte un seminario en el Master en Tecnologías, Sistemas y redes de Comunicaciones, del Departamento de Comunicaciones:
  • Título: Diseño de la capa física en sistemas de comunicaciones digitales

Cursos de formación a empresas

El grupo imparte en el Campus de Gandia de la UPV un curso de especialización dirigido a ingenieros de la industria:

Tesis Doctorales

  • Título: Diseño e implementación en FPGA de Multiplicadores serie/paralelo utilizando aritmética de dígitos en serie y su apliacación al filtrado en tiempo real
    Autor: Javier Valls Coquillat
    Fecha: Octubre 1999

  • Título: Implementación en FPGA de la transformada rápida de Fourier unidimensional y sus operadores básicos con aritmética de dígitos en serie
    Autor: Trinidad Mª Sansaloni Balaguer
    Fecha: Diciembre 2001

  • Título: Implementación en FPGA de la transformada rápida de Fourier con aritmética on-line
    Autor: Asunción Pérez Pascual
    Fecha: Junio 2002

  • Título: Diseño de cores-IP en FPGA de circuitos para transceptores digitales
    Autor: Francisco Cardells Tormo
    Fecha: Octubre 2003

  • Título: Diseño de circuitos para sistemas de comunicaciones WLAN basados en OFDM
    Autor: María José Canet Subiela
    Fecha: Julio 2007

  • Título: Implementación de funciones elementales en dispositivos FPGA
    Autor: Roberto Gutierrez Mazón
    Fecha: Julio 2011

  • Título: Diseño de decodificadores de altas prestaciones para códigos LDPC
    Autor: Fabián Angarita Preciados
    Fecha: Julio 2013

  • Título: Architectures for soft-decision decoding of non-binary codes
    Autor: Francisco Miguel García Herrero
    Fecha: Octubre 2013

  • Título: Implementación VLSI del algoritmo de proyecciones sucesivas para detección de sistemas MIMO
    Autor: José Marín-Roig Ramón
    Fecha: Enero 2016

Publicaciones

    Revistas

  • J.O. Lacruz, F. Garcia-Herrero, M.J. Canet, J. Valls,“Reduced-complexity Non-Binary LDPC decoder for high-order Galois fields based on Trellis Min-Max algorithm, ” IEEE Transactions on Very Large Scale Integration, accepted for publication in 2015
  • J.O. Lacruz, F. Garcia-Herrero, M.J. Canet, J. Valls,“High-performance NB-LDPC decoder with reduction of message exchange, ” IEEE Transactions on Very Large Scale Integration, accepted for publication in 2015
  • J.S. Bruno, V. Almenar, J. Valls, J.L. Corral,“Low-Complexity Time Synchronization Algorithm for Optical OFDM PON System Using a Directly Modulated DFB Laser, ” Journal of Optical Communications and Networking, Vol.7, No. 11, pp.1025-1033, Nov. 2015
  • J.O. Lacruz, F. Garcia-Herrero, J. Valls,“Reduction of complexity for Non-binary LDPC decoders with compressed messages, ” IEEE Transactions on Very Large Scale Integration, Vol.23, No.11, pp.2676-2679, Nov. 2015
  • J.O. Lacruz, F. Garcia-Herrero, D. Declercq, J. Valls, "One Minimum Only Trellis Decoder for Non-Binary Low-Density Parity-Check Codes, " IEEE Transactions on Circuits and Systems I, Vol.62, No.1, pp.177-184, Jan. 2015
  • J.O. Lacruz, F. Garcia-Herrero, D. Declercq, J. Valls, "Simplified Trellis Min-Max Decoder Architecture for Nonbinary Low-Density Parity-Check Codes, " IEEE Transactions on Very Large Scale Integration, Vol.23, No.9, pp.1783-1792, Sep. 2015
  • J.M. Catala, F. Garcia-Herrero, J. Valls, K. Liu, S. Lin, “Reliability-based iterative decoding algorithm for LDPC codes with low variable-node degree, ” IEEE Communications Letters, Vol.18, No.12, pp.2065-2268, Dic. 2014
  • F. Garcia-Herrero, E. Li, D. Declercq, J. Valls, "Multiple-Vote Symbol-Flipping Decoder for Non-Binary LDPC Codes, " IEEE Transactions on Very Large Scale Integration, Vol.22, No.11, pp.2256-2267, Nov. 2014
  • F. Garcia-Herrero, D. Declercq, J.Valls,“Non-Binary LDPC Decoder based on Symbol Flipping with Multiple Votes, ” IEEE Communications Letters, Vol.18 No.5, pp.749-752, Jun.2014
  • F. Angarita, J. Valls, V. Almenar, V. Torres, "Reduced-Complexity Min-Sum Algorithm for Decoding LDPC Codes with Low Error-Floor, ", IEEE Transactions on Circuits and Systems I, Vol.61, No.7, pp.2150-2158, Jul. 2014
  • F. Garcia-Herrero, M.J. Canet, J. Valls, "Non-Binary LDPC Decoder Based on Simplified Enhanced Generalized Bit Flipping Algorithm, " IEEE Transactions on Very Large Scale Integration, Vol.22, No.6, pp.1455-1459, Jun. 2014
  • F. Garcia-Herrero, M.J. Canet, J. Valls, “Architecture of Generalized Bit-Flipping Decoding for High-Rate Non-binary LDPC Codes, ” Circuits, Systems, and Signal Processing, Vol. 32, pp: 727-741, 2013
  • G.A. Jaquenod, J. Valls, J. Siman, “Efficient FPGA Hardware Reuse in a Multiplierless Decimation Chain, ” International Journal of Recon?gurable Computing, accepted for publication in 2013
  • F. Angarita, J. Marin-Roig, V. Almenar, J. Valls, “Low-complexity LDPC decoding algorithm for high-speed VLSI implementation, ” IET Communications, Vol.6, No.16, pp.2575-2581, Nov.2012
  • R. Gutierrez, V. Torres, J.Valls, "Hardware Architecture of a Gaussian Noise Generator Based on Inversion Method, " IEEE Transactions on Circuits & Systems II, Vol. 59, No. 8, pp.501-505, 2012
  • F. Garcia-Herrero, M.J. Canet, J.Valls, M.Flanagan, "Serial Symbol-Reliability Based Algorithm For Decoding Non-Binary LDPC Codes , " IEEE Communications Letters, Vol. 16 No. 6, pp. 909-912, June 2012
  • M.J. Canet, J.Valls, V.Almenar, J. Marin-Roig, "FPGA implementation of an OFDM-based WLAN receiver, " Microprocessors and Microsystems, Vol. 36, No. 3, pp. 232-244, 2012
  • M.J. Canet, V.Almenar, S. Flores, J.Valls, "Low complexity time synchronization algorithm for OFDM systems with repetitive preambles, " Journal of Signal Processing Systems, Vol. 68, No. 3, pp.287-301, Sep. 2012
  • F. Angarita, T.Sansaloni, A. Perez-Pascual, J. Valls, "Modifed Shuffled Based Architecture for High Throughput Decoding of LDPC Codes, " Journal of Signal Processing Systems, Vol. 68, No. 2, pp.139-149, Aug. 2012
  • F. Garcia-Herrero, M.J. Canet, J. Valls, P.K. Meher, "High-Throughput Interpolator Architecture for Low-Complexity Chase Decoding of RS Codes, " IEEE Transactions on Very Large Scale Integration, Vol. 20, No. 3, pp. 568-573, Mar. 2012
  • F. Angarita, T.Sansaloni, M.J.Canet, J. Valls, "Improved Sliced Message Passing Architecture for High Throughput Decoding of LDPC Codes, " Journal of Signal Processing Systems, Vol. 66, No. 2, pp.99-104, Feb. 2012
  • F. Garcia-Herrero, J. Valls, P.K. Meher, "High speed RS(255,239) decoder based on LCC decoding " Circuits, Systems, and Signal Processing, Vol. 30 No. 6 pp.1643-1669, May. 2011
  • R. Gutierrez, J. Valls, "Low cost Hardware Implementation of logarithm approximation ", IEEE Transactions on Very Large Scale Integration, Vol. 19, No. 12, pp. 2326-2330, Dic. 2011
  • R. Gutierrez, V. Torres, J. Valls, "FPGA implementation of atan(Y/X) based on Logarithmic transformation and LUT-based techniques ", Journal of Systems Architecture, Vol. 56, pp. 588-596, Nov. 2010
  • Pramod K. Meher, Javier Valls, Tso-Bing Juang, K. Sridharan, and Koushik Maharatna, "50 Years of CORDIC: Algorithms, Architectures and Applications ", IEEE Transactions on Circuits and Systems I, Vol. 56, No. 9, Sep 2009
  • F. Angarita, A. Almenar, M.J. Canet, T. Sansaloni, J.Valls, "Power consumption reduction in a Viterbi Decoder for OFDM-WLAN ", Journal of Circuits, Systems and Computers Vol. 18, No. 7, pp. 1333-1337, Nov. 2009
  • A. Perez-Pascual, V. Torres, T. Sansaloni, V. Almenar, J.Valls, "Design of Power and Area Efficient Digital Down-converters for Broadband Communications Systems", Journal of Signal Processing Systems Vol. 56, No. 1, pp. 35-40, Jul. 2009
  • R. Gutierrez, J.Valls, "Low-power FPGA-implementation of atan(Y/X) using Look-Up Table methods for communication applications", Journal of Signal Processing Systems Vol. 56, No. 1, pp. 26-33, Jul. 2009
  • V. Torres, A. Perez-Pascual, T. Sansaloni, J.Valls, "Design and FPGA-implementation of a high performance timing recovery loop for broadband communications", Journal of Signal Processing Systems Vol. 56, No. 1, pp. 17-23, Jul. 2009
  • F. Angarita, M.J. Canet, T. Sansaloni, A. Perez-Pascual, J.Valls, "Efficient mapping of CORDIC Algorithm for OFDM-based WLAN", Journal of Signal Processing Systems, Vol. 52, No. 2, pp. 181-191, Aug. 2008
  • F. Angarita, M.J. Canet, T. Sansaloni, V. Almenar, J.Valls, "Architectures for the implementation of a OFDM-WLAN Viterbi Decoder", Journal of Signal Processing Systems, Vol. 52, No. 1, pp. 35-44, Jul. 2008
  • T. Sansaloni, A. Perez-Pascual, V. Torres, J.Valls, "Scheme for reducing the storage requirements of FFT twiddle factors on FPGAs", Journal of VLSI Signal Processing, Vol. 47, pp. 105-115, May. 2007
  • T. Sansaloni, A. Perez-Pascual, V. Torres, V. Almenar, J. Toledo, J.Valls, "FFT Spectrum Analyser Project for Teaching Digital Signal Processing with FPGA devices", IEEE Trans. on Education, November 2007
  • J.Valls, T. Sansaloni, A. Perez-Pascual, V. Torres, V. Almenar, "The use of CORDIC in Software Defined Radios: A tutorial", IEEE Communications Magazine, vol. 44, no. 9, September 2006
  • T. Sansaloni, A. Perez-Pascual, V. Torres, J. Valls, "Efficient pipeline FFT processor form MIMO-OFDM systems", Electronic Letters, Vol. 41, No. 19, September 2005
  • T. Sansaloni, A. Perez-Pascual, J. Valls, "Area-efficient FPGA-based FFT processor", Electronic Letters, Vol. 39, No. 19, September 2003
  • J. Valls and E. Boemo, "Efficient FPGA-Implementation of two's complement digit-serial/parallel multipliers", IEEE Trans. on Circuits and Systems II, vol. 50, no. 6, June 2003
  • F. Cardells, J. Valls, "Area-Optimized Implementation of Quadrature Direct Digital Frequency Synthesizers on LUT-based FPGAs", IEEE Trans. on Circuits and Systems II, vol. 50, no. 3, March 2003
  • T. Sansaloni, J. Valls, K.K. Parhi, "Digit-serial Complex-Number Multipliers on FPGAs", Journal of VLSI Signal Processing, special issue on Computer Arithmetic and Applications,  Vol. 33, Nos. 1-2,  pp. 105-115, Jan. 2003
  • J. Valls, M. Kuhlmann, K.K. Parhi, "Evaluation of CORDIC Algorithms for FPGA design", Journal of VLSI Signal Processing, Vol. 32, No. 3.  pp. 207-222, Nov 2002
  • F. Cardells, J. Valls, "Optimisation of direct digital frequency synthesizers  based on CORDIC", Electronic Letters, Vol. 37, No. 21, pp. 1278-1280, October 2001


    Congresos

  • F. Garcia-Herrero, D. Declercq, J. Valls, “ A symbol flipping decoder for NB-LDPC relying on multiple votes, ” 2014 8th International Symposium on Turbo Codes and Iterative Information Processing (ISTC), Bremen, Germany, Aug.2014
  • E. Li, D. Declercq, F. Garcia-Herrero, J. Omar, J. Valls, “ Low latency T-EMS decoder for NB-LDPC codes, ” Asilomar Conference on Signals, Systems and Computers, Pacific Grove, CA, USA, Nov.2013
  • F Garcia-Herrero, MJ. Canet, J. Valls, “ High-speed NB-LDPC decoder for wireless applications, ” Int.Symposium on Intelillent Signal Processing and Communication Systems (ISPACS), Okinawa, Japan, Nov.2013
  • F Garcia-Herrero, MJ. Canet, J. Valls, “ Decoder for an Enhanced Serial Generalized Bit Flipping Algorithm, ” IEEE International Conference on Electronics, Circuits and Systems (ICECS), Sevilla, Spain, Dec.2013
  • V. Torres, A. Perez-Pascual, T. Sansaloni, J. Valls, “Fully-parallel LUT-based (2048,1723) LDPC Code Decoder for FPGA, ” IEEE International Conference on Electronics, Circuits and Systems (ICECS), Sevilla, Spain, Dec.2012
  • F. Angarita, V. Torres, A. Perez-Pascual, J. Valls, “High-Throughput FPGA-based Emulator for Structured LDPC Codes, ” IEEE International Conference on Electronics, Circuits and Systems (ICECS), Sevilla, Spain, Dec.2012
  • F. Garcia-Herrero, M.J. Canet, J. Valls, “Decoder for an Enhanced Serial Generalized Bit Flipping Algorithm, ” IEEE International Conference on Electronics, Circuits and Systems (ICECS), Sevilla, Spain, Dec.2012
  • R. Gutierrez, J. Valls, A. Perez-Pascual, "FPGA-implementation of time-multiplexed multiple constant multiplication based on carry-save arithmetic" International Conference in Field Programmable Logic and Applications (FPL2009), Prague, Czech Republic Aug. 2009
  • J. Marín-Roig, V. Almenar, M.J. Canet, J. Valls, "64-QAM 4x4 MIMO Decoders Based on Successive Projection Algorithm" IEEE International Conference on Electronics, Circuits and Systems (ICECS 2008), Malta, Aug. 2008
  • F. Angarita, M.J. Canet, T. Sansaloni, V. Almenar and J. Valls, "Reduction of power consumption in a Viterbi Decoder for OFDM-WLAN" IEEE International Conference on Electronics, Circuits and Systems (ICECS 2007), Marrakech, Morocco, Dec. 2007
  • A. Pérez-Pascual, T. Sansaloni, V. Torres, V. Almenar and J. Valls, "Design of an efficient digital down-converter for a SDR-based DVB-S receiver" European Conference on Circuit Theory and Design (ECCTD 2007), Sevilla, Spain, Aug. 2007
  • M.J. Canet, V. Almenar, J. Marin-Roig, J. Valls, "Time synchronization for the IEEE 802.11a/g WLAN Standard ", 8th IEEE Annual International Symposium on Personal Indoor and Mobile Radio Communications (PIMRC 2007), Athens, Greece, Sept. 2007
  • M.J. Canet, V. Almenar, S. Flores, J. Valls, "Improvement of a Time Synchronization Algorithm for IEEE 802.11a/G WLAN Standard", 15th European Signal Processing Conference (EUSIPCO2007), Poznan, Poland, Sept. 2007
  • R. Gutierrez, J. Valls, "Implementation on FPGA of a LUT-based atan(Y/X) operator suitable for Synchronization Algorithms", International Conference in Field Programmable Logic and Applications (FPL2007), Amsterdam, Holland, Aug. 2007
  • V. Torres, T. Sansaloni, A. Perez-Pascual, J. Valls, "Design of high performance timing recovery loops for communication applications", 2006 IEEE Workshop on Signal Procesing Systems (SiPS 2006), Banff, Canada, Nov. 2006
  • M.J.Canet, I. Wassel, V. Almenar, J. Valls, "Performance evaluation of fine time synchronizer for WLANs", 13th european Conference on Signal Processing (EUSIPCO 2005), Sept. 2005, Antalya, Turkey
  • F. Angarita, T. Sansaloni, A. Pérez-Pascual, J. Valls, "FPGA-based design of a Viterbi decoder for WLAN", 2005 IEEE Workshop on Signal Procesing Systems (SiPS 2005), Atenas, Grecia, Nov. 2005
  • F. Angarita, T. Sansaloni, A. Pérez-Pascual, J. Valls, "Efficient FPGA implementation of CORDIC algorithm for circular and linear coordinates", International Conference in Field Programmable Logic and Applications (FPL2005), Tampere, Finland, Ago. 2005
  • T. Todorovich, E. Boemo, F. Angarita, J. valls, "Statical power estimation for FPGAs", International Conference on Field Programmable Logic and Applications (FPL2005), Tampere, Finland, Ago. 2005
  • MJ.Canet, F. Vicedo, V. Almenar, J. Valls, "FPGA implementation of an IF transceiver for OFDM-based WLAN", 2004 IEEE Workshop on Signal Processing Systems (SiPS 2004), Aug. 2004, Austin, Texas
  • M.J.Canet, F. Vicedo, V. Almenar, J. Valls, E.R. De Lima, "Hardware Design of a FPGA-Based Synchronizer for Hiperlan/2", International Conference in Field Programmable Logic and Applications (FPL2004), Aug. 2004, Antwerp, Belgium
  • MJ. Canet, F. Vicedo, J. Valls, V. Almenar, "A common FPGA-based synchronizer architecture for hiperlan 2 and IEEE 802.11A WLAN systems", 15th International Symposium on Personal, Indoor and Mobile Radio Communications (PIMRC 2004), Sept. 2004, Barcelona, Spain
  • M.J.Canet, F. Vicedo, V. Almenar, J. Valls, E.R. De Lima, "Implementation of a Synchronizer for Hiperlan/2 on FPGA", International  Workshop on Telecommunications (IWT04) Santa Rita do Sapucai, MG, Brazil, August 24-26, 2004
  • MJ. Canet, F. Vicedo, J. Valls, V. Almenar, "Design of a digital front-end transmitterfor OFDM-WLAN systems using FPGA", First International Symposium on Control, Communications and Signal
  • Processing (ISCCSP 2004), March 2004, Hammamet, Tunisia
  • F. Cardells, J. Valls, "Quadrature Direct Digital Frequency Synthesizers: Area-optimized Design Map for LUT-based FPGAs", IEEE International Symposium on Circuits and Systems (ISCAS2003)
  • J. Marín-Roig, V.Torres, M.J.Canet, A.Pérez, T. Sansaloni, F. Cardells, F.Angarita, F.Vicedo, V.Almenar, J.Valls, "DIGIMOD: A tool to implement FPGA-based digital IF and baseband modems", 13th International Conference on Field Programmable Logic and Applications, FPL 2003, Sept. Lisbon, Portugal
  • F. Cardells, J. Valls, V. Almenar, "Symbol Timing Synchronization in FPGA-based Software Radios: Application to DVB-S", 13th International Conference on Field Programmable Logic and Applications (FPL 2003), Sept. Lisbon, Portugal
  • F. Cardells, A. Perez-Pascual, V. Torres, J. Valls, V. Almenar, "Design of a DVB-S receiver in FPGA", 2003 IEEE Workshop on Signal Procesing Systems (SiPS 2003), Aug. 2003, Seoul Korea
  • J. Marín-Roig, V.Torres, M.J.Canet, A.Pérez, T. Sansaloni, F. Cardells, F.Angarita, F.Vicedo, V.Almenar, J.Valls, "DIGIMOD: A tool to implement FPGA-based digital front-end for software radios", 2003 Software Defined Radio Technical Conference and Product Exposition (SDR03), Nov. Orlando, Florida
  • F. Cardells, J. Valls, V. Almenar, V. Torres, "Efficient FPGA-based QPSK Demodulation Loops: Application to the DVB standard",12th international Conference on Field Programmable Logic and Applications (FPL 2002), Sept. Montpellier, France
  • F. Cardells, J. Valls, "High Performance Quadrature Digital Mixers for FPGAs", 12th international Conference on Field Programmable Logic and Applications (FPL 2002), Sept. Montpellier, France
  • José Marin-Roig, Javier Valls, Vicenç Almenar, "LUT-based Up-converters for FPGA", Communication Systems, Networks and Digital Signal Processing Conference, July 2002
  • F. Cardells, J. Valls, "Optimized FPGA-implementation of quadrature DDS", IEEE International Symposium on Circuits and Systems (ISCAS2002), May 2002, AZ USA
  • A. Perez-Pascual, T. Sansaloni, J. Valls, "FPGA Based Radix-4 Butterflies for HIPERLAN/2", IEEE International Symposium on Circuits and Systems (ISCAS2002),  May 2002, AZ USA
  • T. Sansaloni, A. Perez-Pascual, J. Valls, "Distributed Arithmetic Radix-2 Butterflies for FPGA", International IEEE Conference on Electronics, Circuits, and Systems (ICECS 2001)
  • A. Perez-Pascual, T. Sansaloni, J. Valls, "FPGA Based On-line Complex-Number Multipliers", International IEEE Conference on Electronics, Circuits, and Systems (ICECS 2001)
  • J. Valls, M. Kuhlmann, K.K. Parhi, Efficient mapping of CORDIC algorithms on FPGA", 2000 IEEE Workshop on Sijgnal Processing Systems (SiPS2000), Oct. 2000, Louisiana, USA
  • T. Sansaloni, J. Valls, K.K. Parhi, Digit-Serial Fixed Coefficient Complex Number Multiplier-Accumulator on FPGAs", 13th Annual  IEEE International ASIC/SOC Conference, Sept. 2000, Washington
  • T. Sansaloni, and J. Valls, "FPGA-Based Digit-Serial Radix 2 Butterflies", IASTED International Conference Signal Processing and Communications (SPC 2000), Marbella, September 2000.
  • A. Pérez-Pascual, and J. Valls, "Radix-4 On-Line Complex-Number Multiplier", IASTED International Conference Signal Processing and Communications (SPC 2000), Marbella, September 2000.
  • T. Sansaloni, J. Valls, K.K. Parhi,FPGA-based Digit-Serial Complex Number Multiplier-Accumulator”, IEEE International Symposium on Circuits and Systems (ISCAS2000), May 2000, Geneva.
  • J.Valls, T.Sansaloni, M.M.Peiró, E.Boemo, Fast FPGA-Based Pipelined Digit-Serial/Parallel Multipliers, IEEE International Symposium on Circuits and Systems (ISCAS'99), Orlando, Junio 1999.
  • A.P. Pascual, J.Valls, M. Martínez, Efficient Complex-Number Multipliers mapped on FPGA”, 6th IEEE International Conference on Electronics, Circuits and Systems (ICECS´99), Chipre, Sep 1999.>
  • T. Sansaloni, J.Valls, M.J. Canet, M. Martínez , FPGA-based notch filter for cancelling 50Hz noise on ECGs, XIII Design of Circuits and Integrated Systems Conference (DCIS´99), Mallorca 1999.
  • M. M. Peiró, J. Valls, T. Sansaloni , A.P. Pascual, E. Boemo, A Comparison between Lattice, Cascade and Direc-form FIR Filter Structures by using an FPGA Bit-serial Distributed Arithmetic Implementation”, 6th IEEE International Conference on Electronics, Circuits and Systems (ICECS´99), Chipre,  Sep 1999.
  • J.Valls, M. Martínez, T. Sansaloni, E. Boemo, Design and FPGA implementation of Digit-Serial FIR filters”, 5th IEEE International Conference on Electronics, Circuits and Systems (ICECS´98), Lisboa 1998.
  • J.Valls, M. Martínez, T. Sansaloni, E. Boemo, A Study About FPGA-based Digital Filters, 1998 IEEE Workshop on Signal Processing Systems: Design and Implementation (SiPS'98), Boston 1998.
  • J.Valls, M. Martínez, T. Sansaloni, E. Boemo, “Custom Digit-Serial DSPs on Altera FPGAs”, XIII Design of Circuits and Integrated Systems Conference (DCIS´98), Madrid  1998.
  • M. Martínez, J.Valls,  T. Sansaloni, E. Boemo, “High-Level Synthesis of Custom DSP Blocks using Distributed Arithmetic”, XIII Design of Circuits and Integrated Systems Conference (DCIS´98), Madrid 1998.
  • M. Martínez, J.Valls, E. Boemo, “On the design of PFGA-based multioperand pipeline adders”, XII Design of Circuits and Integrated Systems Conference (DCIS´97), Sevilla 1997.


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